Probing Semiconductor 中文 / EN / 日本語 / 한국어 Submit a request

Memory and HBM: pin count, channels and touchdown force

On a whole-wafer touchdown, an HBM card has almost twenty times the pins of a base card type. This article explains how pin count affects tester channels, test coverage and chuck force.

Technical articleFor NAND, NOR, DRAM and HBM probe cardsRelated equipment: PCT5801 · DeepTouch1000

The device sets the pin count

The pin count of a probe card is set by the device under test. A memory probe card touches down on the whole wafer at once: 16,000 pins for the base card type and 60,000 pins for a DRAM card. For an HBM card, the pin count is almost twenty times that of the base card type.

The card-side pin capacity of the current PCT5801 platform is 67,000 pins. Cards at DRAM and HBM level are designed individually for card type, motherboard and tester interface. Pin counts in this article all mean card-side pin count.

Pins needed by the device on a whole-wafer touchdown: base card type 16,000, DRAM card 60,000, HBM card almost twenty times the base card type; the blue dashed line is the current PCT5801 platform card-side pin capacity of 67,000Pins needed by the device · whole-wafer touchdownBase card type16,000DRAM card60,000HBM cardAlmost 20×Current PCT5801 platform card-side pin capacity: 67,000
Pins needed by the device on a whole-wafer touchdown: base card type 16,000, DRAM card 60,000, HBM card almost twenty times the base card type; the blue dashed line is the current PCT5801 platform card-side pin capacity of 67,000Pins needed by the device · whole-wafer touchdownBase card type16,000DRAM card60,000HBM cardAlmost 20×Current PCT5801 platformcard-side pin capacity: 67,000
Schematic: bar lengths are drawn in proportion to the pins the device needs; the blue dashed line is the card-side pin capacity of the current PCT5801 platform.

Four quantities on one chain

Four quantities sit on one chain: card-side pin count, matrix nodes, tester channels and instrument resources.

Four quantities on one chain: card-side pin count 67,000 pin (current PCT5801 platform capacity) → matrix nodes 65,536 (1,024 per board × up to 64 boards) → tester channels 16,384 (standard; maximum configuration 65,536) → instrument resources (PMU, DPS and digital units, set by the units fitted)Probe cardPCT5801 test systemPMUDPSDigital unitCard-side pin count67,000 pinCurrent PCT5801 platform capacitySet by the device under testMatrix nodes65,5361,024 per board × 64 maxSwitched in turn, not togetherTester channels16,384Standard configurationMaximum 65,536Instrument resourcesBy configurationPMU · DPS · digital unitsSet by the units fittedDifferent bases; not interchangeable
Four quantities on one chain: card-side pin count 67,000 pin (current PCT5801 platform capacity) → matrix nodes 65,536 (1,024 per board × up to 64 boards) → tester channels 16,384 (standard; maximum configuration 65,536) → instrument resources (PMU, DPS and digital units, set by the units fitted)Card-side pin count67,000 pinCurrent PCT5801 platform capacitySet by the device under testMatrix nodes65,5361,024 per board × 64 maxSwitched in turn, not togetherTester channels16,384Standard configurationMaximum 65,536PMUDPSDigital unitInstrument resourcesBy configurationPMU · DPS · digital unitsSet by the units fittedDifferent bases; not interchangeable
Schematic: numbers are from the current PCT5801 platform.

Pins and scan paths

Card-side pin count and scan paths are two different quantities; definitions are on the terms page.

Card-side pin count →Scan paths →

Channels and instrument resources

The basis for tester channels and instrument resources is defined on the terms page.

Tester channels →Instrument resources →

Test coverage down to every pin

PCT5801 runs open, short, leakage and AC tests on all pins or all channels. Leakage is tested pin to pin on all pins, with a criterion of 10 nA.

The channel capacity of the relay matrix expands with pin-count needs, and task time varies with pin count and configuration. An electrical anomaly is mapped to its coordinate on the card, and probe-tip XYZ, force and contact state then explain the physical cause.

The control signal test verifies MCW, FPGA, ASIC, I²C and SPI control resources. Analog measurement uses the Kelvin four-wire method, with DPS device power.

Open test schematic: all pins floating, continuity checked along each channelAll pins floating
OpenAll pins floating; continuity checked on every channel.
Short test schematic: all pins touch a shorting plate, channel-to-channel shorts checkedShorting plate
ShortAll pins touch a shorting plate; shorts between channels are checked.
Leakage current test schematic: pin-to-pin test, criterion 10 nA10 nACriterion
LeakageAll-pin pin-to-pin test, criterion 10 nA.
Control signal test schematic: FPGA, ASIC and relay control resources on the card verified through MCW, SPI and I²CMCW · SPI · I²CFPGAASICRelay
Control signalVerifies MCW, FPGA, ASIC, I²C and SPI control resources.
AC test schematic: TDR transmission-time measurement on signal channelsTransmission time
AC TDRTransmission time is measured on all signal channels.
Probe-tip 3D inspection schematic: length, position and planarity measured for every pinXZYPlanarity
Tip XYZDeepTouch1000 inspects pin length, position and planarity in 3D.
Schematic: the first five are done by PCT5801 and tip XYZ by DeepTouch1000; pin count and proportions are not to scale.
Screenshot of the PCT5801 main test screen: open resistance and leakage current listed pin by pin by DUT, ZIF and pin position
PCT5801 main test screen · screenshot

Every pin is recorded

The main test screen lists every pin by DUT, ZIF and pin position. Open resistance and leakage current are each judged once, producing a traceable report.

PCT5801 product details →View in the hall →

Whole-card touchdown and chuck force

On a whole-wafer touchdown, all pins of the card make contact at once. The total load depends on the number of pins in simultaneous contact, force per pin, overdrive and safety factor.

High-pin-count cards are limited by chuck force on general-purpose probers such as the UF3000 and P-12XL. DeepTouch1000 was developed for this, with a chuck force of 1,000 kgf, measured at full load.

Loaded in steps to 1,000 kgf, Z-axis straightness is < 0.2 µm. Chuck flatness deviation is ≤ 10 µm (3 mm stroke), and the three loading runs gave consistent results.

The final supported pin count is confirmed per card type and FAT/SAT plan.

Whole-card simultaneous contact schematic: the chuck presses from below; total load depends on pins in contact, force per pin, overdrive and safety factorProbe cardChuckChuck forcePins in contactForce per pinoverdriveTotal load depends on:pins in contact · force per pin · overdrive · safety factor
Chuck force comparison: DeepTouch1000 chuck force 1,000 kgf, measured at full loadChuck force · kgf01,000DeepTouch10001,000 kgf · measured at full loadAbout 9.81 kNGeneral-purpose probers such as UF3000, P-12XL:high-pin-count cards limited by chuck force
Schematic: the touchdown drawing is not to scale; bar lengths in the chuck force comparison are drawn to scale.

Related products

Terms and definitions →
PCT5801 probe card test systemEnd-to-end electrical test covering open, short, 10 nA leakage and TDR. DeepTouch1000 dedicated probe stationWhole-card touchdown at 1,000 kgf chuck force, with 3D probe-tip XYZ inspection. Probe card motherboardsDesigned for the tester platform and card type, with DC and TDR AC test.

Please provide card type, pin count and tester platform

We will acknowledge receipt within one business day.

Send a request