PCT5801 probe card electrical test platform and motherboard rack

Modular high-channel electrical inspection

PCT5801 Probe Card Electrical Test Platform

PCT5801 sits between the ATE/tester and probe card motherboard. Its 1,024-channel modules, ZIF/POGO interfaces and test recipes handle open, short, leakage, control-resource and selected high-speed checks.

Motherboard and channel rack in a real system. Interface and quantity depend on project configuration.
Channel module1,024 ch / pieceScales with system size
Current system16,384 channelsHigh-channel test configuration
InterfacesZIF / POGODesigned around motherboard and fixture
CoverageDC + control + optional high speedTest items selected per project
Equipment and engineering solution

Applications

Designed for the following probe card manufacturing, test and maintenance tasks.

Release and post-repair test

Check opens, shorts, leakage and control resources with a traceable report.

Pre-ATE interface validation

Verify motherboard, channel and basic electrical state before occupying a production tester.

High-channel expansion

Organize capacity around 1,024-channel modules and scale for the card and rack configuration.

SPECIFICATIONS

Specifications

The final configuration follows the card, interfaces, site conditions and acceptance items.

ItemSpecification / configurationNotes
System positionATE/tester → PCT5801 channel/relay → motherboard → probe cardInterface definitions match the actual boards
Module capacity1,024 channels / pieceModule count follows target channels, rack and interface configuration
Core itemsOpen, Short and LeakageLimits and ranges follow sample evaluation and the technical agreement
Control itemsMCW, Relay, FPGA, ASIC, SPI and I²CEnabled by resource configuration
Optional itemsAC, TDR, PBDATA and KelvinRequire corresponding hardware and interfaces
Mechanical interfacesZIF, POGO and project fixturesMotherboard structure and changeover are project-defined
DataConfiguration version, raw result, judgement and retest recordSupports reporting, traceability and FAT/SAT
WORKFLOW

Workflow

01

Define channel mapping

Create a consistent relationship from tester, motherboard and probe card pin map.

02

Load task configuration

Set item, range, limit, control resources and retest strategy.

03

Execute and localize

Run tests and locate anomalies to a channel, motherboard or probe-card position.

04

Publish reviewable results

Preserve raw data, version and judgement; route physical anomalies to DeepTouch when needed.

FAT / SAT

Project delivery

01

Sample evaluation

Confirm the object, interfaces, current state, failure modes and available validation samples.

02

Technical agreement

Define configuration, measurement method, limits, takt, data interfaces and responsibilities.

03

FAT

Verify functions, repeatability, reporting and exception handling with agreed samples.

04

SAT

Complete site integration, training, upstream/downstream interfaces and issue closure.

CONFIGURATION

Configuration and acceptance

System configuration, optional items and acceptance conditions are summarized below.

System configuration

The current high-channel system supports 16,384 channels.

Modular design

1,024-channel modules are combined for the rack, motherboard and required tests.

Parameter definition

Ranges, limits, high-speed items and Kelvin coverage are set during sample evaluation and technical agreement.

Share the card, interfaces and target

Send the sample, installed equipment, current issue and target takt. We will acknowledge receipt within one business day.