Technology route · not a product for sale
CMOS Image Sensor Test Solution
The bottleneck in image sensor testing is the image data itself: with large frames and many sites, shipping data back to the workstation consumes the takt. This solution gives each site on the EVA100 platform an APU (Acceleration Processing Unit) image board: frames are captured over MIPI CSI-2 or DVP and the algorithms run locally at the site, with no upload to the workstation and full site independence. The content comes from the solution chapter of a 2022 training document; it is a technology route, not a product for sale, and the test-item list and delivery form are not yet defined.
Category visual, not an actual EVA100. The solution hardware form follows the actual engineering definition.
Equipment and engineering solution
Applications
The technology route covers the following application directions.
Multi-site parallel CIS testing
Each site processes its own image data, avoiding the communication cost of centralized upload - especially suited to trim-style operations.
Image-interface capture
Capture over MIPI CSI-2 D-PHY with 1/2/4 data lanes; DVP 10/12-bit and LVDS are possible extensions, covering the RGB, YUV and RAW format families.
Local algorithm execution
Under demo conditions, algorithms on 3264 x 2464 images across 8 frames run in about 100 ms.
SPECIFICATIONS
Specifications
The final configuration follows the device interface, image format, site count and engineering conditions.
| Item | Specification / configuration | Notes |
|---|---|---|
| Solution stage | Technology route, not a product for sale | From the solution chapter of a 2022 training document; test items and delivery form undefined |
| System architecture | EVA100 tester + per-site Image Board (APU) + controlled light source | Ethernet links the tester and the image boards |
| APU composition | AI multi-core processor + flexible FPGA logic | Per site: quad Arm 64-bit cores + 128 GPU cores, upgradable to 256/512 |
| Compute | 400 GFLOPS, upgradable to 20 TFLOPS | Core is a mature AI SoC from a large fabless company |
| Memory | 4 GB DDR per site, 25.6 G/s bandwidth (as documented) | Upgradable to 8 GB at 51.2 G/s |
| Image interface | MIPI CSI-2 D-PHY: 1/2/4 data lanes + 1 clock lane, up to 1.5 Gbps/lane | Upgradable to 2.5 Gbps/lane; DVP 10/12-bit and LVDS are listed as possible in the source |
| Image formats | RGB888/666/565; YUV422-8b/444-8b; RAW6/7/8/10/12/14 | Configured to the device output format |
| Software stack | EVA test sequences / image-processing API / light-source API / APU driver | Runs on the EVA100 system software |
| Demo result | 3264 x 2464, 8 frames, algorithm time approx. 100 ms | Demo conditions as stated in the training document |
| Route direction | D-PHY toward 2.5 Gbps/lane; C-PHY toward 2.5 Gsym/s per trio | The documented roadmap dates are from 2021; current status requires engineering confirmation |
WORKFLOW
Workflow
Device and interface confirmation
Typical flow once a project starts: confirm the sensor output interface, image format and site count.
APU and light-source configuration
Configure image boards, the controlled light source and EVA100 resources per site count.
Algorithm and sequence development
Image-processing algorithms deploy on the APU; test sequences run on the EVA100.
Solution validation
Validate takt and data path with demos and samples, then define the delivery form.
PROJECT OUTLINE
Prospective project delivery
Requirement and device evaluation
Confirm the sensor interface, image format, site count and target takt.
Technical agreement
Define the solution scope, hardware composition, algorithm boundary and responsibilities.
Solution validation
Validate the data path and takt with samples and demos.
Delivery definition
Define the delivery form and acceptance based on validation results.
CONFIGURATION
Configuration and acceptance
The sections below describe the solution's sources, ownership boundary and undefined items.
Source and stage
Content comes from the CMOS image sensor solution chapter of a 2022 EVA100 training document (system architecture, APU specification and demo data); the documented roadmap dates are from 2021, so this page presents a technology route, with no claim of a product for sale.
Ownership boundary
The solution is built on the Advantest EVA100 platform; the engineering owner of the image board (APU) is not stated in the source, so this page makes no in-house-development claim.
Undefined items
The test-item list, judgment methods and delivery form are not defined in the source and must be established per engineering project.
Share the device interface, image format and target
Send the sample, installed equipment, current issue and target takt. We will acknowledge receipt within one business day.