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In development

CMOS image sensor test solution

The solution puts one APU image-processing board at each site, and images are processed locally at the site.

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Hall model of the EVA100 tester cable-connection station Model rendering, not an actual EVA100

Key figures

Memory · per site
4GB DDRBandwidth 25.6 G/s (as documented)
Image interface
1.5GbpsPer lane · MIPI CSI-2 D-PHY
Compute · per site
400GFLOPSQuad Arm cores + 128 GPU cores
Demo processing time
About 100ms3264 × 2464 · 8 frames

Compute placed at the site

The bottleneck in image sensor test is the image data: once frames get large and sites multiply, shipping every frame back to a workstation eats the takt. This solution puts an image board at each site on the EVA100 platform and runs the algorithm locally, so sites do not wait on one another.

Solution architecture diagram: the EVA100 tester connects over Ethernet to the Image Board (APU) at each site; each image board captures from that site's image sensor over MIPI CSI-2 or DVP, under a controlled light source EVA100 tester EVA test sequences · light-source API · image-processing API Ethernet Image Board (APU) Site 1 · local algorithm Image Board (APU) Site 2 · local algorithm Image Board (APU) Site n · local algorithm Sites fully independent MIPI CSI-2 / DVP Image sensor Image sensor Image sensor Controlled light source at each site · image formats RGB / YUV / RAW
Illustration: drawn from the system architecture in the 2022 EVA100 training document; the solution hardware form follows the actual engineering definition.

Applications

Multi-site parallel CIS testing

Each site processes its own image data, avoiding the communication cost of centralized upload, especially suited to trim-style operations.

Image-interface capture

Capture over MIPI CSI-2 D-PHY with 1/2/4 data lanes; DVP 10/12-bit and LVDS are possible extensions, covering the RGB, YUV and RAW format families.

Local algorithm execution

Under demo conditions, algorithms on 3264 × 2464 images across 8 frames run in about 100 ms.

Defined per project

The test-item list, judgment methods and delivery form are established per engineering project.

How a project proceeds (illustrative)

  1. Device and interface confirmationConfirm the sensor output interface, image format, site count and target takt.
  2. APU and light-source configurationConfigure image boards, the controlled light source and EVA100 resources per site count.
  3. Algorithm and sequence developmentImage-processing algorithms deploy on the APU; test sequences run on the EVA100.
  4. Solution validationValidate takt and data path with demos and samples, then define the delivery form.

Specifications

The final configuration follows the device interface, image format, site count and engineering conditions.

Full specification table (9 items)
ItemSpecification / configurationNotes
System architectureEVA100 tester + per-site Image Board (APU) + controlled light sourceEthernet links the tester and the image boards
APU compositionAI multi-core processor + flexible FPGA logicPer site: quad Arm 64-bit cores + 128 GPU cores, upgradable to 256/512
Compute400 GFLOPS, upgradable to 20 TFLOPSCore is a mature AI SoC from a large fabless company
Memory4 GB DDR per site, 25.6 G/s bandwidth (as documented)Upgradable to 8 GB at 51.2 G/s
Image interfaceMIPI CSI-2 D-PHY: 1/2/4 data lanes + 1 clock lane, up to 1.5 Gbps/laneUpgradable to 2.5 Gbps/lane; DVP 10/12-bit and LVDS are listed as possible in the source
Image formatsRGB888/666/565; YUV422-8b/444-8b; RAW6/7/8/10/12/14Configured to the device output format
Software stackEVA test sequences / image-processing API / light-source API / APU driverRuns on the EVA100 system software
Demo result3264 × 2464, 8 frames, algorithm time approx. 100 msDemo conditions as stated in the training document
Route directionD-PHY toward 2.5 Gbps/lane; C-PHY toward 2.5 Gsym/s per trioThe documented roadmap dates are from 2021; current status requires engineering confirmation

Content comes from the CMOS image sensor solution chapter of a 2022 EVA100 training document (system architecture, APU specification and demo data); the delivery form is defined per project. Items not listed follow the technical agreement.

The solution is built on the Advantest EVA100 platform. EVA100 is Advantest's product; Probing is its representative and distributor. The name is used only to identify the platform the solution applies to and does not indicate authorisation, certification or endorsement by the maker. The engineering owner of the image board (APU) is not stated in the source, so this page makes no in-house-development claim.

Related pages

Advantest EVA100 application and test engineeringThe Advantest EVA100 digital and mixed-signal test system, and test-program development. Test and validationPCT5801, DeepTouch1000, adapter motherboards and PSTA20K. PSTA20K socket testerUses EVA100 as the test front end, for package sockets beyond 5,000 channels.

Give the engineering team the device interface, image format and targets

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