Probing Semiconductor
Semiconductor test system equipment visual (not an actual EVA100)

Digital and mixed-signal test system · E-Model / P-Model

Advantest EVA100 Application and Test Engineering

EVA100 is Advantest's digital and mixed-signal test system for characterization, performance evaluation and production test, offered as the E-Model (engineering) and P-Model (production). As its representative and distributor, Probing develops test programs around the actual boards and device specifications, covering CP, FT, IP validation and failure analysis with Sequence, Timing, Level, Device Block, virtual instruments and Shmoo.

Submit a project requestSee it on the floorView related equipment
Category visual, not an actual EVA100; the actual appearance follows the Advantest catalogue. Boards, instrument resources and software capability follow the actual system configuration.
ModelsE-Model / P-Model
Digital channels128ch to 1024ch
Per-pin resourcesPPMU −1.25 to +7 V, ±32 mA
Analog and HV±64 V / ±128 V / 1000 V
The same points in words
Models
Engineering / production configurations
Digital channels
100 Mbps, double clock 200 MHz
Per-pin resources
64 channels per DM64 module
Analog and HV
AVI · MVI · HVI modules
Equipment and engineering solution

Applications

Designed for the following test and engineering tasks.

Device test-program development

Engineering validation and failure analysis

CP/FT flow migration

The same points in words
Device test-program development
Build test items and limits for MCU, logic, PMIC and sensor devices from the specification, boards and test resources.
Engineering validation and failure analysis
Locate voltage, current, timing and margin issues with virtual instruments, sequences and Shmoo.
CP/FT flow migration
Organize equipment resources, interface boards, test programs and data output into an acceptable migration.
SPECIFICATIONS

Specifications

The final configuration follows the card, interfaces, site conditions and acceptance items.

System modelsE-Model engineering; P-Model productionTesting units: 1 on E-Model; up to 4 on P-Model
Digital channelsE-Model 128ch (DM64 x 2); P-Model 256 to 1024ch100 Mbps base rate, double clock 200 MHz
Pattern memory128 MW; SCAN channel linking up to 2 GWWith subroutine, fail-analysis and digital-capture memories
Resources per DM64PPMU 64ch (−1.25 to +7 V, ±32 mA); DPS 4ch (−6 to +7 V, −400 to +500 mA); VPP 16ch up to 13.5 V; TMU 8ch to 200 MHzPlus PDPS 64ch (−1.25 to +7 V, ±64 mA, parallel operation), CPMU, 18-bit AWG/DGT and a reference source
Analog source/measureAVI 6ch: ±64 V or −32 to +96 V, up to ±500 mA; MVI 2ch: ±128 V, current measure up to 5 A; HVI 1ch: 1000 V floatingMinimum current-measure resolution 62.5 pA on AVI/MVI
Waveform generate and captureLF: AWG 200 ksps/24-bit, DGT 625 ksps/24-bit; HF: AWG 512 Msps/16-bit, DGT 250 Msps/16-bitHF sine 0.1 Hz to 200 MHz, up to 6 Vpp, distortion below −100 dB at 1 MHz
See the full specification table
ItemSpecification / configurationNotes
OscilloscopeSCAP 4ch: 1 Gsps, 500 MHz bandwidth (PB direct 50 ohm; 300 MHz on the 1 Mohm BNC input), 8,000 samples per channelHigh-speed mode 2 Gsps on 2ch
Protocols and controlI2C, SPI, JTAG and arbitrary protocols; GCM 8ch with register-map device controlOptions add SENT, PSI5, CAN/CANFD/LIN
Power and control interfaceE-Model: 100-240 V single phase, PCIe; P-Model: 200 V single phase, optical interfaceACDC Box feeds the testing unit at 48 V DC
Size and weightTesting unit Mini 220 x 472 x 206 mm / Standard 363 x 472 x 206 mm, approx. 8.2-19.4 kgACDC Box, AC-CONT and workstation listed separately
Target devicesMCU, small FPGA/ASIC, standard logic, fingerprint IC, digital sensors, Flash, plus LDO, DC-DC and op-amp analog devicesDigital and analog modules combine per configuration examples
SoftwareMeasurement Atelier; options include System Software Pro, STILReader Plus, CATVert VCD and production-environment toolsWindows 10 with graphical development and debug
Engineering deliveryEnvironment check, interface boards, programs, golden samples, reports and trainingScope is defined in the technical agreement
WORKFLOW

Workflow

  1. 01

    System and device inventory

  2. 02

    Test-item and resource mapping

  3. 03

    Program development and debug

  4. 04

    Golden sample and delivery

The same points in words
System and device inventory
Check the EVA100 configuration, boards, interfaces, device specification and existing programs.
Test-item and resource mapping
Map specification items to power, digital, mixed-signal and clock resources.
Program development and debug
Verify with sequences, timing, levels, device blocks and Shmoo.
Golden sample and delivery
Check results against known samples, then complete reports, version control and on-site training.
FAT / SAT

Project delivery

01

Sample evaluation

02

Technical agreement

03

FAT

04

SAT

The same points in words
Sample evaluation
Confirm the object, interfaces, current state, failure modes and available validation samples.
Technical agreement
Define configuration, measurement method, limits, takt, data interfaces and responsibilities.
FAT
Verify functions, repeatability, reporting and exception handling with agreed samples.
SAT
Complete site integration, training, upstream/downstream interfaces and issue closure.
CONFIGURATION

Configuration and acceptance

System configuration, optional items and acceptance conditions are summarized below.

Parameter source

Hardware parameters on this page come from Advantest's public EVA100 catalogue (Bulletin No. EVA100-A11C, January 2020, Simplified Chinese edition); the catalogue notes that specifications and appearance may change without notice.

Built versus represented

EVA100 is Advantest's product; Probing is its representative and distributor and provides mechanical integration, application engineering and test-program development.

Configuration confirmation

Actual boards, instrument resources and software functions follow the target system as installed; delivery scope is defined in the technical agreement.

Share the card, interfaces and target

Send the sample, installed equipment, current issue and target takt. We will acknowledge receipt within one business day.

Submit a project requestPSTA20K Ultra-High-Channel Socket Tester