Product
Memory probe card test for the HBM era.
This workflow is built around one-touchdown memory probe card test, high pin counts, tester-side realism, and an integrated electrical plus physical validation path.
HBM-era demand
Probe card electrical test built for dense memory workflows.
This one-touchdown probe card test workflow is built to simulate actual mass-production wafer test conditions rather than act as a generic analyzer.
Full-wafer, one-touchdown context
Targets NAND / NOR / DRAM memory tester workflows where pin count can move from 16,000 to 60,000 and further toward 300,000 in HBM-style contexts.
Control-resource validation
Relay, FPGA, ASIC, MCW, SPI, and I²C related control checks are part of the intended workflow rather than side tasks.
System, not analyzer
The design concept is explicit: build a probe card test system that fits tester, prober, and test-interface environments and helps customers solve real problems first.
Connected physical layer
Electrical test alone is not enough.
The same workflow extends into the physical side through DeepTouch1000, where contact performance, tip consistency, and wafer-sort handling matter.
DeepTouch1000 integration
PB5801 all-in-one operation combines with 1000 kgf chuck force and needle-tip inspection support.
Tester and station ecosystem
Supported probers include UF3000, UF3000ex, TEL Precio, SEMICS OPUS3, and CNS.
Application-driven engineering
The product shape comes from long-term application experience around testers, probers, and test interfaces, with a strong problem-first bias.