High-channel electrical and physical validation
Memory Probe Card Test System
Built for NAND, NOR, DRAM and HBM probe cards, the system connects PCT5801 electrical testing, tester/prober interfaces and DeepTouch1000 physical inspection in one flow for post-build, post-repair and high-pin-count release checks.
PCT5801 high-channel system. The current configuration supports 16,384 channels; motherboard and interfaces are designed for the target card.
Equipment and engineering solution
Applications
Designed for the following probe card manufacturing, test and maintenance tasks.
Memory probe card release
Build a traceable result set around Open, Short, Leakage, control resources and interface checks after manufacture or repair.
HBM and one-touchdown evaluation
Review channel organization and one-touchdown paths around the high-pin-count motherboard and tester/prober ecosystem.
Electrical anomaly localization
Locate open, short, leakage or control anomalies, then use tip XYZ, load and contact evidence to investigate physical causes.
SPECIFICATIONS
Specifications
The final configuration follows the card, interfaces, site conditions and acceptance items.
| Item | Specification / configuration | Notes |
|---|---|---|
| Applications | NAND, NOR and DRAM; HBM configured by project | Probe card, motherboard and tester define the system configuration |
| Core electrical checks | Open, Short and nA-level Leakage | Limits, ranges and coverage are set in the technical agreement |
| Control resources | MCW, Relay, FPGA, ASIC, SPI and I²C | Enabled according to board and tester interfaces |
| High-speed / waveform items | PBDATA, TDR and AC | Optional items requiring corresponding hardware and interfaces |
| Channel scale | Current 16,384-channel system | 60k/300k HBM are expansion designs configured for the target card |
| Typical task time | Open 5 min; Short 5 min; 10k-pin / 10 nA Leakage 60 min; MCW/control 5-30 min; PBDATA/TDR 20 min | Varies with card type, channel configuration, judgement logic and retest strategy |
| Tester ecosystem | T5830, T5833, M5 and V93000 P16 | Interfaces follow the on-site tester, motherboard and project documents |
| Prober ecosystem | UF3000/UF3000ex, TEL Precio, SEMICS OPUS3 and CNS | Mechanical, electrical and automation interfaces are confirmed per project |
WORKFLOW
Workflow
Model samples and interfaces
Confirm card type, pin count, tester, prober, motherboard, control resources and acceptance items.
Run electrical tests
Execute Open, Short, Leakage, MCW, control and selected high-speed items while retaining raw results.
Correlate physical checks
Inspect probe-tip XYZ, load, probe mark or contact state at anomalous locations.
Report and retest
Retain configuration versions, results, disposition and retest conclusions for FAT/SAT.
FAT / SAT
Project delivery
Sample evaluation
Confirm the object, interfaces, current state, failure modes and available validation samples.
Technical agreement
Define configuration, measurement method, limits, takt, data interfaces and responsibilities.
FAT
Verify functions, repeatability, reporting and exception handling with agreed samples.
SAT
Complete site integration, training, upstream/downstream interfaces and issue closure.
CONFIGURATION
Configuration and acceptance
System configuration, optional items and acceptance conditions are summarized below.
Installed systems
Product records include more than 10 systems in mainland China and one in Korea.
Expansion design
16,384 channels is the current system configuration. 60k/300k HBM systems are designed around the target card, motherboard and tester interface.
Project definition
Final channel count, range, limits, interfaces and task time are set through sample evaluation, project documents and FAT/SAT.
Share the card, interfaces and target
Send the sample, installed equipment, current issue and target takt. We will acknowledge receipt within one business day.