Test and validationPCT5801 · DeepTouch1000 · motherboards · PSTA20K
Probe assemblyProbe placement and laser micro-welding
Cleaning and reinspectionCleaning and three-direction reinspection
Smart storageStorage and traceability
Prober servicesInformation box · uP200A · pre-owned equipment
Probe-card hallMEMS probe-card manufacturing and validation · 21 stations
CP hallProbers, tester docking and retrofits of installed probers · 17 stationsECP1010Embedded-chip IC substrate test machine
This machine runs fully automatic electrical test on embedded-chip PCBs, with 1,024 channels measured directly.
Design rendering, not a built machineKey figures
- Test channels
- 1,024channelsMeasured directly · expanded to 16,384 through a relay matrix
- Substrate size
- 200 × 500mmCustomizable · brochure figure
- Motion speed
- 1,500mm/sAcceleration 1.2 G
- Transport accuracy
- ±0.05mmBrushless DC linear motors
A chip embedded in the PCB, tested for function from the surface pads
Once the IC is embedded inside the PCB, the only accessible test points are the pads on the board surface. Production lines currently use ICT for open/short, leakage and specified LRC checks, which cannot cover device-level functional test. ECP1010 has a built-in ATE test unit that runs parametric and functional tests on the embedded digital and analog chips.
- 01Stack loading and interleaf removal
Batch substrates separate automatically; interleaving paper is removed on loading.
- 02Vision alignment and press-down
CCD alignment followed by press-down contact establishes the test connection.
- 03ATE electrical test
Digital and analog board resources run the parametric and functional test items.
- 04Marking and unloading
Results link to the 2D code; after laser marking, substrates unload with interleaving paper re-inserted.
Applications
Embedded-chip substrate electrical test
Run batch parametric and functional tests on PCB substrates with embedded digital and analog chips.
Process validation and fault isolation
Use ATE-grade board resources for device parameters and function items, and trace failures to the specific substrate.
Traceability and marking
Link results through 2D-code identification and finish with automatic laser marking.
Stage
Four design documents from 2023-06 to 2024-07 show the specification still iterating, with no delivery or acceptance records. The images on this page are design renderings.
Specifications
Specifications follow the 2023-06 public brochure; the design iteration direction of the 2024-07 proposal is listed separately.
Full specification table (14 items)
| Item | Specification / configuration | Notes |
|---|---|---|
| Product stage | In development, design and engineering stage | No production delivery records; specifications iterate with the design |
| Test object | Embedded-chip PCB substrates | Electrical and functional test of the embedded digital and analog chips |
| Substrate size | 200 × 500 mm, customizable | Thickness 0.08-1.2 mm (brochure figures) |
| Contact method | Probe-card fixture with double-sided press-down contact | Proposal documents also describe a single-side full-face contact configuration |
| Test channels | 1,024 channels measured directly | Expanded to 16,384 channels through a relay matrix |
| Motion system | Brushless DC linear motors on a monolithic frame | 1500 mm/s, 1.2 G acceleration, transport accuracy ±0.05 mm |
| Vision and marking | One CCD set with 2D-code reading | Automatic laser-marking unit (added in the 2024-07 proposal) |
| Built-in ATE · digital | 1,024 channels, 200 MHz, 128 M vector depth | Digital driver/comparator boards: −1.25 to +7 V, ±32 mA, 18-bit waveform generation and capture |
| Built-in ATE · analog and HV | Analog, medium-power and high-voltage source-measure configured per test item | Module specifications are provided in the technical agreement |
| Built-in ATE · waveform | LF 24-bit: 200 ksps AWG / 625 ksps DGT; HF 16-bit: 512 Msps AWG / 250 Msps DGT | Oscilloscope board 1 Gsps, 500 MHz, 8,000 sample points |
| Protocols | I2C, SPI, JTAG and arbitrary protocols | Configured per device specification |
| Software | Graphical sequence programming, vector edit and debug, logic analysis, virtual instruments, Shmoo, VI-curve reports, STILReader, CATVert-VCD | Production control panel, GPIB driver editor, real-time result reports |
| Facilities (proposal figures) | AC 380 V three-phase 50 Hz, approx. 8 kW | Approx. 1550 x 1400 x 1700 mm, approx. 1200 kg |
| Design iteration direction | 2024-07 proposal: substrate range 45 x 50 to 95 x 240 mm, thickness 0.1-2 mm; alignment accuracy ±5 μm (single side); minimum pad 0.15 mm at 0.2 mm pitch | Coexists with the brochure figures; the technical agreement decides the final values |
The board resources of the built-in ATE test unit follow the design documents; test items, limits and the final configuration are set in the technical agreement.
Project delivery
- Sample evaluationConfirm the object, interfaces, current state, failure modes and available validation samples.
- Technical agreementDefine configuration, measurement method, limits, takt, data interfaces and responsibilities.
- FAT (factory acceptance)Verify functions, repeatability, reporting and exception handling with agreed samples.
- SAT (site acceptance)Complete site integration, training, upstream/downstream interfaces and issue closure.
Related pages
Give the engineering team the substrate, interfaces and targets
Send your samples, installed equipment, current issue and target takt, and we will acknowledge receipt within one business day.